SSD Controllers

What does the controller do?

We list controllers separately because they are pivotal for the performance characteristics of every SSD. It is effectively the central processing unit (CPU) of the drive and sits between the host interface – SATA or PCIe – and the NAND flash chips, handling every read and write operation that the drive performs. Its responsibilities fall into a few broad areas.

Flash management. NAND degrades with use. Each program/erase (p/e) cycle wears out the cells, and the controller manages this through wear leveling. Wear leveling means distributing writes across the full capacity of the drive so no single block wears down disproportionately. Related to this is garbage collection: NAND cannot overwrite data in place, so the controller must periodically consolidate valid data and erase free blocks in the background to keep write performance predictable. Write amplification — the ratio of data actually written to NAND versus what the host requested — is a direct measure of how efficiently the controller handles this process.

Error correction. Another problem with NAND flash is that it produces read errors, and more so as it ages. The controller runs an ECC (error-correcting code) engine to detect and repair bit errors before they reach the host. Modern TLC and QLC NAND requires stronger ECC than older MLC drives, which is one reason controller complexity has increased over time. LDPC (low-density parity-check) codes replaced the older BCH codes in most controllers from around 2015 onward.

Host interface and queuing. SATA controllers implement the AHCI protocol; NVMe controllers speak directly to the PCIe bus and support deep command queues — up to 65,535 commands across 65,535 queues versus AHCI's single queue of 32. This is the main architectural reason why NVMe drives show lower latency under mixed workloads, regardless of whether the underlying NAND is faster.

Caching and DRAM. Most enterprise and high-end consumer controllers include an on-board DRAM chip (separate from the NAND) to store the flash translation layer (FTL) mapping table. The FTL maps logical block addresses as seen by the host to physical locations in NAND, accounting for the fact that those locations change constantly as data moves during wear leveling and garbage collection. Holding this map in fast DRAM reduces read latency. Budget controllers omit separate DRAM and either store the map in a reserved portion of the NAND (HMB designs borrow a slice of host RAM instead) or use a simplified mapping scheme at the cost of random-write performance.

Controller families and vendor relationships. A given controller model is typically used by many SSD brands under different product names. Phison, Silicon Motion, and Marvell sell their designs to drive manufacturers who pair them with NAND sourced from Micron, Kioxia, or Samsung. As a result, drives from Sabrent, Seagate, Corsair and others are often built on identical silicon. The meaningful differences between such drives come from NAND sourcing, firmware tuning, and thermal design rather than the controller itself. Samsung, Western Digital, and Kioxia (and historically Intel) are notable exceptions as they design their own controllers in-house, giving them tighter control over the full signal path from host to cell.